A.5.290 SHL, SHR: Bitwise Logical Shifts
SHL r/m8,1 ; D0 /4 [8086]
SHL r/m8,CL ; D2 /4 [8086]
SHL r/m8,imm8 ; C0 /4 ib [186]
SHL r/m16,1 ; o16 D1 /4 [8086]
SHL r/m16,CL ; o16 D3 /4 [8086]
SHL r/m16,imm8 ; o16 C1 /4 ib [186]
SHL r/m32,1 ; o32 D1 /4 [386]
SHL r/m32,CL ; o32 D3 /4 [386]
SHL r/m32,imm8 ; o32 C1 /4 ib [386]
SHR r/m8,1 ; D0 /5 [8086]
SHR r/m8,CL ; D2 /5 [8086]
SHR r/m8,imm8 ; C0 /5 ib [186]
SHR r/m16,1 ; o16 D1 /5 [8086]
SHR r/m16,CL ; o16 D3 /5 [8086]
SHR r/m16,imm8 ; o16 C1 /5 ib [186]
SHR r/m32,1 ; o32 D1 /5 [386]
SHR r/m32,CL ; o32 D3 /5 [386]
SHR r/m32,imm8 ; o32 C1 /5 ib [386]
SHL and SHR perform a logical shift operation on the given
source/destination (first) operand. The vacated bits are filled with
zero.
A synonym for SHL is SAL (see section A.5.283). NASM will assemble
either one to the same code, but NDISASM will always disassemble that
code as SHL.
The number of bits to shift by is given by the second operand. Only the
bottom five bits of the shift count are considered by processors above
the 8086.
You can force the longer (186 and upwards, beginning with a C1 or
C0 byte) form of SHL foo,1 by using a BYTE prefix: SHL foo,BYTE 1.
Similarly with SHR.