A.5.288 SFENCE: Store Fence
SFENCE ; 0F AE /7 [KATMAI]
SFENCE performs a serialising operation on all writes to memory that
were issued before the SFENCE instruction. This guarantees that all
memory writes before the SFENCE instruction are visible before any
writes after the SFENCE instruction.
SFENCE is ordered respective to other SFENCE instruction, MFENCE, any
memory write and any other serialising instruction (such as CPUID).
Weakly ordered memory types can be used to achieve higher processor
performance through such techniques as out-of-order issue, write-
combining, and write-collapsing. The degree to which a consumer of
data recognizes or knows that the data is weakly ordered varies among
applications and may be unknown to the producer of this data. The
SFENCE instruction provides a performance-efficient way of insuring
store ordering between routines that produce weakly-ordered results and
routines that consume this data.
SFENCE uses the following ModR/M encoding:
Mod (7:6) = 11B
Reg/Opcode (5:3) = 111B
R/M (2:0) = 000B
All other ModR/M encodings are defined to be reserved, and use of these
encodings risks incompatibility with future processors.
See also LFENCE (section A.5.137) and MFENCE (section A.5.151).