A.5.137 LFENCE: Load Fence
LFENCE ; 0F AE /5 [WILLAMETTE,SSE2]
LFENCE performs a serialising operation on all loads from memory that
were issued before the LFENCE instruction. This guarantees that all
memory reads before the LFENCE instruction are visible before any reads
after the LFENCE instruction.
LFENCE is ordered respective to other LFENCE instruction, MFENCE, any
memory read and any other serialising instruction (such as CPUID).
Weakly ordered memory types can be used to achieve higher processor
performance through such techniques as out-of-order issue and
speculative reads. The degree to which a consumer of data recognizes or
knows that the data is weakly ordered varies among applications and may
be unknown to the producer of this data. The LFENCE instruction provides
a performance-efficient way of ensuring load ordering between routines
that produce weakly-ordered results and routines that consume that data.
LFENCE uses the following ModR/M encoding:
Mod (7:6) = 11B
Reg/Opcode (5:3) = 101B
R/M (2:0) = 000B
All other ModR/M encodings are defined to be reserved, and use of these
encodings risks incompatibility with future processors.
See also SFENCE (section A.5.288) and MFENCE (section A.5.151).