A.5.62 DIVSD: Scalar Double-Precision FP Divide
DIVSD xmm1,xmm2/mem64 ; F2 0F 5E /r [WILLAMETTE,SSE2]
DIVSD divides the low-order double-precision FP value in the destination
operand by the low-order double-precision FP value in the source
operand, and stores the double-precision result in the destination
register.
The destination is an XMM register. The source operand can be either an
XMM register or a 64-bit memory location.
dst[0-63] := dst[0-63] / src[0-63],
dst[64-127] remains unchanged.