A.5.28 CMPccSD: Scalar Double-Precision FP Compare
CMPSD xmm1,xmm2/mem64,imm8 ; F2 0F C2 /r ib [WILLAMETTE,SSE2]
CMPEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 00 [WILLAMETTE,SSE2]
CMPLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 01 [WILLAMETTE,SSE2]
CMPLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 02 [WILLAMETTE,SSE2]
CMPUNORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 03 [WILLAMETTE,SSE2]
CMPNEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 04 [WILLAMETTE,SSE2]
CMPNLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 05 [WILLAMETTE,SSE2]
CMPNLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 06 [WILLAMETTE,SSE2]
CMPORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 07 [WILLAMETTE,SSE2]
The CMPccSD instructions compare the low-order double-precision FP
values in the source and destination operands, and returns the result
of the comparison in the destination register. The result of each
comparison is a quadword mask of all 1s (comparison true) or all 0s
(comparison false).
The destination is an XMM register. The source can be either an XMM
register or a 128-bit memory location.
The third operand is an 8-bit immediate value, of which the low 3 bits
define the type of comparison. For ease of programming, the 8 two-
operand pseudo-instructions are provided, with the third operand already
filled in. The "Condition Predicates" are:
EQ 0 Equal
LT 1 Less-than
LE 2 Less-than-or-equal
UNORD 3 Unordered
NE 4 Not-equal
NLT 5 Not-less-than
NLE 6 Not-less-than-or-equal
ORD 7 Ordered
For more details of the comparison predicates, and details of how to
emulate the "greater-than" equivalents, see section A.2.3