NASM 2.05 based x86 Instruction Reference[ch040]
A.5.21 CLFLUSH: Flush Cache Line CLFLUSH mem ; 0F AE /7 [WILLAMETTE,SSE2] CLFLUSH invalidates the cache line that contains the linear address specified by the source operand from all levels of the processor cache hierarchy (data and instruction). If, at any level of the cache hierarchy, the line is inconsistent with memory (dirty) it is written to memory before invalidation. The source operand points to a byte-sized memory location. Although CLFLUSH is flagged SSE2 and above, it may not be present on all processors which have SSE2 support, and it may be supported on other processors; the CPUID instruction (section A.5.34) will return a bit which indicates support for the CLFLUSH instruction.