A.5.8 AND: Bitwise AND
AND r/m8,reg8 ; 20 /r [8086]
AND r/m16,reg16 ; o16 21 /r [8086]
AND r/m32,reg32 ; o32 21 /r [386]
AND reg8,r/m8 ; 22 /r [8086]
AND reg16,r/m16 ; o16 23 /r [8086]
AND reg32,r/m32 ; o32 23 /r [386]
AND r/m8,imm8 ; 80 /4 ib [8086]
AND r/m16,imm16 ; o16 81 /4 iw [8086]
AND r/m32,imm32 ; o32 81 /4 id [386]
AND r/m16,imm8 ; o16 83 /4 ib [8086]
AND r/m32,imm8 ; o32 83 /4 ib [386]
AND AL,imm8 ; 24 ib [8086]
AND AX,imm16 ; o16 25 iw [8086]
AND EAX,imm32 ; o32 25 id [386]
AND performs a bitwise AND operation between its two operands (i.e. each
bit of the result is 1 if and only if the corresponding bits of the two
inputs were both 1), and stores the result in the destination (first)
operand. The destination operand can be a register or a memory location.
The source operand can be a register, a memory location or an immediate
value.
In the forms with an 8-bit immediate second operand and a longer first
operand, the second operand is considered to be signed, and is sign-
extended to the length of the first operand. The BYTE qualifier can be
used to force NASM to generate this form of the instruction. Recent
versions of NASM automatically optimise to this form if the immediate
operand's value is known during the assembling of that instruction, and
fits in the range of a signed byte. The longer variant can then still be
forced using the STRICT WORD or STRICT DWORD qualifier.
The Carry Flag is cleared by AND. The Zero Flag is set according to
whether the result is zero.
The TEST (see section A.5.317) instruction performs the same operation
as AND but without writing to the destination operand. That is, it only
reads the operands and writes the status flags.
The MMX instruction PAND (see section A.5.202) performs the same
operation on the 64-bit MMX registers.