A.2.5.3 TF - Trace flag
If set, the CPU will invoke the Trace interrupt (interrupt 1) after the
next instruction. There are a few special cases:
- Other interrupt invocations ignore the prior Trace flag status. That
is, interrupts are not traced.
- After an interrupt invocation, the IRET (see section A.5.127)
restores TF=1, but the Trace interrupt is then only called after
another instruction. That is, the Trace interrupt "fires too late".
- When interrupt lockout due to MOV or POP to SS is in effect, no
Trace interrupt is invoked.
- When a repeated string operation is invoked, at most one iteration
is executed. (E)IP is reset in case more iterations are to be
executed.
If (E)CX was greater than 1, and (for CMPSx and SCASx) after the
first comparison the Zero flag is set or clear so as to repeat the
operation, the (E)IP address is reset to point to the first prefix
opcode and then a Trace interrupt is invoked.
When (E)CX was 1 prior to the instruction, or the Zero flag after
the comparison indicates to break out of the repetition, then one
iteration is executed, (E)IP is not reset, and a Trace interrupt is
invoked.
When (E)CX was 0 prior to the instruction, then no iteration
is executed, but (E)IP is still incremented to point after the
instruction, and a Trace interrupt is invoked.