A.2 Key to Opcode Descriptions
This appendix also provides the opcodes which NASM will generate for
each form of each instruction. The opcodes are listed in the following
way:
- A hex number, such as 3F, indicates a fixed byte containing that
number.
- A hex number followed by "+r", such as "C8+r", indicates that one
of the operands to the instruction is a register, and the "register
value" of that register should be added to the hex number to produce
the generated byte. For example, EDX has register value 2, so the
code "C8+r", when the register operand is EDX, generates the hex
byte CA. Register values for specific registers are given in section
A.2.1.
- A hex number followed by "+cc", such as "70+cc", indicates that
the instruction name has a condition code suffix, and the numeric
representation of the condition code should be added to the hex
number to produce the generated byte. For example, the code "70+cc",
when the instruction contains the "NE" condition, generates the hex
byte 75. Condition codes and their numeric representations are given
in section A.2.2. In one case, "70+(cc^1)" is given, which means
that the inverse condition code is encoded in the byte.
- A slash followed by a digit, such as "/2", indicates that one of the
operands to the instruction is a memory address or register (denoted
"mem" or "r/m", with an optional size). This is to be encoded as an
effective address, with a ModR/M byte, an optional SIB byte, and an
optional displacement, and the spare (register) field of the ModR/M
byte should be the digit given (which will be from 0 to 7, so it
fits in three bits). The encoding of effective addresses is given in
section A.2.6.
- The code "/r" combines the above two: it indicates that one of the
operands is a memory address or "r/m", and another is a register,
and that an effective address should be generated with the spare
(register) field in the ModR/M byte being equal to the "register
value" of the register operand. The encoding of effective addresses
is given in section A.2.6; register values are given in section A.
2.1.
- The codes "ib", "iw" and "id" indicate that one of the operands
to the instruction is an immediate value, and that this is to be
encoded as a byte, little-endian word or little-endian doubleword
respectively.
- The codes "rb", "rw" and "rd" indicate that one of the operands to
the instruction is an immediate value, and that the _difference_
between this value and the address of the end of the instruction is
to be encoded as a byte, word or doubleword respectively. Where the
form "rw/rd" appears, it indicates that either "rw" or "rd" should
be used according to whether assembly is being performed in BITS 16
or BITS 32 state respectively.
- The codes "ow" and "od" indicate that one of the operands to the
instruction is a reference to the contents of a memory address
specified as an immediate value: this encoding is used in some forms
of the MOV instruction in place of the standard effective-address
mechanism. The displacement is encoded as a word or doubleword.
Again, "ow/od" denotes that "ow" or "od" should be chosen according
to the BITS setting.
- The codes "o16" and "o32" indicate that the given form of the
instruction should be assembled with operand size 16 or 32 bits.
In other words, "o16" indicates a 66 prefix in BITS 32 state, but
generates no code in BITS 16 state; and "o32" indicates a 66 prefix
in BITS 16 state but generates nothing in BITS 32.
- The codes "a16" and "a32", similarly to "o16" and "o32", indicate
the address size of the given form of the instruction. Where this
does not match the BITS setting, a 67 prefix is required. Please
note that "a16" is useless in long mode as 16-bit addressing is
depreciated on the x86-64 architecture extension.