A.1 Key to Operand Specifications
The instruction descriptions in this appendix specify their operands
using the following notation:
- Registers: "reg8" denotes an 8-bit general purpose register, "reg16"
denotes a 16-bit general purpose register, "reg32" a 32-bit one and
"reg64" a 64-bit one. "fpureg" denotes one of the eight FPU stack
registers, "mmxreg" denotes one of the eight 64-bit MMX registers,
and "segreg" denotes a segment register. "xmmreg" denotes one of
the 8, or 16 in x64 long mode, SSE XMM registers. In addition, some
registers (such as AL, DX, ECX or RAX) may be specified explicitly.
- Immediate operands: "imm" denotes a generic immediate operand.
"imm8", "imm16" and "imm32" are used when the operand is intended
to be a specific size. For some of these instructions, NASM allows
an explicit specifier: for example, ADD ESP,16 could be interpreted
as either ADD r/m32,imm32 or ADD r/m32,imm8. If the immediate value
is known during the assembling of that instruction, and fits in the
range of a signed byte, then recent versions of NASM automatically
optimise the instruction by choosing the latter form. It is allowed
to specify ADD ESP,BYTE 16 explicitly, which is needed to indicate
that optimisation in case the immediate value is not known by NASM.
(Eg, if it is a symbol reference only resolved by the linker.)
Conversely, using the qualifiers STRICT WORD or STRICT DWORD
forces NASM to use the longer forms. There is a special case of
the allowance of an "imm64" for particular x64 versions of the MOV
instruction.
- Memory references: "mem" denotes a generic memory reference;
"mem8", "mem16", "mem32", "mem64" and "mem80" are used when the
operand needs to be a specific size. Again, a specifier is needed
in some cases: DEC [address] is ambiguous and will be rejected by
NASM. You must specify DEC BYTE [address], DEC WORD [address] or
DEC DWORD [address] instead.
- Restricted memory references: one form of the MOV instruction allows
a memory address to be specified _without_ allowing the normal range
of register combinations and effective address processing. This is
denoted by "memoffs8", "memoffs16", "memoffs32" or "memoffs64".
- Register or memory choices: many instructions can accept either a
register _or_ a memory reference as an operand. "r/m8" is shorthand
for "reg8/mem8"; similarly "r/m16" and "r/m32". On legacy x86 modes,
"r/m64" is MMX-related, and is shorthand for "mmxreg/mem64". When
utilizing the x86-64 architecture extension, "r/m64" denotes use of
a 64-bit GPR as well, and is shorthand for "reg64/mem64".